Titlebook: Analog Integrated Circuit Design Automation; Placement, Routing a Ricardo Martins,Nuno Lourenço,Nuno Horta Book 2017 Springer International

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Empirical-Based Parasitic Extractor,ion, and the intercap models provided by the foundry that contain the standard interconnect capacitance values. This Chapter explains all the methods used in the empirical-based Parasitic Extractor to accurately compute the parasitic structures, from the processing of the intercap models tables to t

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AIDA-L: Architecture and Integration,ask, using the proposed AIDA-L tool. AIDA-L is integrated in an in-house analog IC design automation framework, AIDA (Martins et al., International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Sep 2015, pp. 1–4), for complete automati

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Template-Based Placer,described in a XML template file to a non-slicing B*-tree layout representation (Chang et al., Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC), 2000, pp. 458–463). Then, the B*-tree is packed using the modules, which are instantiated from the AIDA’s analog module generator (AIDA-

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Optimization-Based Placer, presented in Chapter 4 of this book, the optimization-based Placer dispenses most of the information contained in the template file. Instead, it applies a multi-objective algorithm to an absolute floorplan representation in order to determine the cells’ locations. Cells can be organized in proximit

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Fully-Automatic Router,of electric-current values for each terminal contained in the netlist. The solution space is then automatically explored, minimizing the total wiring area and complying with a set of electromigration, IR-Drop and wiring symmetry constraints. The Router ensures that each wire does not violate any of