Titlebook: Analog Circuit Design; High-Speed A-D Conve Arthur H.M. Van Roermund,Herman Casier,Michiel Ste Book 2006 Springer Science+Business Media B.

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22GS/s ADCs – IMPLEMENTATION CHOICES AND PERFORMACE TRADE-OFFSImplementation options for very high speed ADCs are discussed by first reviewing performance limiting mechanisms then comparing the various architectures and building blocks typically used in these converters. Results for a 5b 22GS/s ADC are presented.

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CONCEPTS AND IMPROVEMENTS IN PIPELINE AND SAR ADCSIn this paper we want to review the development of pipelined and SAR ADCs from basic concepts to novel techniques. We will demonstrate that there are quite a lot of similarities and that there are a few major discrepancies. Based on this we draw comparisons and point out specific strengths and weaknesses of the individual architectures.

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FAST AND POWER-EFFICIENT CMOS SUBRANGING ADCsThis paper presents a two-step subranging ADC architecture based on interpolation, averaging, offset compensation and pipelining techniques. Application of these techniques results in fast and power-efficient converters with an accuracy between 8b and 12b.

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Book 2006cs....Analog Circuit Design. is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest developments in the field. The tutorial coverage also makes it suitable for use in an advanced design course..

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Krankheiten der Leber und Gallenwege,to excessive loop delays and to DAC waveform asymmetry, and a higher tolerance to clock imperfections. The proposed SDM ADC offers an alternative to low-speed low-performance low-cost and high-speed high-performance and high-cost implementations by introducing a new trade-off between limit cycle frequency and clock frequency.

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A Bartsch,M Fischer,U Zollingerransceiver, regulatory requirements of the Medical Implantable Communication Service (MICS) band, provides a description of a product competing in this arena and a unique crystal startup circuit that can significantly reduce power consumption in power critical implant applications.

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SUB-HARMONIC LIMIT-CYCLE SIGMA-DELTA MODULATION, APPLIED TO AD CONVERSIONto excessive loop delays and to DAC waveform asymmetry, and a higher tolerance to clock imperfections. The proposed SDM ADC offers an alternative to low-speed low-performance low-cost and high-speed high-performance and high-cost implementations by introducing a new trade-off between limit cycle frequency and clock frequency.