| 期刊全称 | A Practical Approach to VLSI System on Chip (SoC) Design | | 期刊简称 | A Comprehensive Guid | | 影响因子2023 | Veena S. Chakravarthi | | 视频video | http://file.papertrans.cn/142/141774/141774.mp4 | | 发行地址 | A comprehensive practical guide for VLSI designers.Covers end-to-end VLSI SoC design flow.Includes source code, case studies, and application examples | | 图书封面 |  | | 影响因子 | .This book provides a comprehensive overview of the VLSI design process. It covers end-to-end system on chip (SoC) design, including design methodology, the design environment, tools, choice of design components, handoff procedures, and design infrastructure needs. The book also offers critical guidance on the latest UPF-based low power design flow issues for deep submicron SOC designs, which will prepare readers for the challenges of working at the nanotechnology scale. This practical guide will provide engineers who aspire to be VLSI designers with the techniques and tools of the trade, and will also be a valuable professional reference for those already working in VLSI design and verification with a focus on complex SoC designs..A comprehensive practical guide for VLSI designers;.Covers end-to-end VLSI SoC design flow;.Includes source code, case studies, and application examples.. | | Pindex | Book 20201st edition |
| 1 |
Front Matter |
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Abstract
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| 2 |
,Introduction, |
Veena S. Chakravarthi |
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Abstract
This chapter introduces VLSI technology; trends in terms of integrated circuit complexity, performance, power, and physical size; and the future direction. It also describes challenges posed by emerging trends on design methodology to make it work a first time success. It introduces the concept of a . and how it differentiates with VLSI as a .. The chapter also sets the basic design context in terms of resources, skill set required, and EDA environment for design of a . and lists the overall challenges in SOC design.
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| 3 |
,System on Chip (SOC) Design, |
Veena S. Chakravarthi |
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Abstract
This chapter deals with introduction to system on chip (SOC), constituents of SOC and few examples of SOCs, followed by SOC development cycle, design planning, design requirements, the design center infrastructure, design and verification intellectual properties IPs, and design flows of different constituents of SOC. The chapter contains some of the VLSI processes like synthesis, DFT, and physical design which will be described in further chapters in detail. The reader should take these terms as intermediate processes in chip design till explained in detail.
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| 4 |
,SOC Constituents, |
Veena S. Chakravarthi |
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Abstract
This chapter deals with major constituents of typical system on chip (SOC) with their relevance, criteria for choosing the right cores to integrate in SOC, and design challenges they throw during SOC design integration.
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| 5 |
,VLSI Logic Design and HDL, |
Veena S. Chakravarthi |
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Abstract
This chapter discusses different VLSI design techniques highlighting coding style for synthesis. It covers important design concepts like synchronous and asynchronous circuits, clock and reset circuits, clock domain crossovers, speed matching, and so on. In addition, it deals with behavioral modelling, structural modelling, standard cell libraries, and different file formats generated during design phases with SOC design context. The reader is advised to refer VLSI logic design books (A Verilog HDL primer, J Bhaskar; VHDL primer Jayaram Bhaskar, A System Verilog primer, J Bhaskar) for fundamental understanding of VLSI design and books on hardware description languages like Verilog and VHDL for clear understanding and mastering them.
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| 6 |
,SOC Synthesis, |
Veena S. Chakravarthi |
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Abstract
This chapter deals with the synthesis of SOC, detailing the strategies adopted for synthesis of different constituents of SOC. It also deals with standard cell library selection, SOC design constraints, Synthesis optimization, Synthesis report generation, intrepretation of the reports and some useful guidelines to get desired SOC design performance.
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| 7 |
,Static Timing Analysis (STA), |
Veena S. Chakravarthi |
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Abstract
This chapter explain the timing analysis techniques, tools for timing analysis, concept of design corners, challenges of on-chip variations in advanced technology nodes, and a few tips to address those challenges for achieving SOC timing closure.
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| 8 |
,SOC Design for Testability (DFT), |
Veena S. Chakravarthi |
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Abstract
This chapter describes requirement for testability, the design for testability (DFT) of SOC. It explains the methodology widely followed for SOC DFT and the automatic test pattern generation (ATPG) techniques. It covers the major challenges faced during SOC design in the context of DFT. This chapter introduces the concept of compression and need for test optimization to reduce ATE test times and its impact on economics of SOC.
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| 9 |
,SOC Design Verification, |
Veena S. Chakravarthi |
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Abstract
This chapter deals with the importance of SOC design verification, plan and strategies adopted for verification. It defines functional simulation, functional coverage, code coverage, and other important terms used in verification. Importance of FPGA validation and how it complements the SOC design verification is explained in this chapter. Most of the simulation concept of SOC design verification explained in the chapter can be seen in the verification of the reference designs provided in Chapter 12.
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| 10 |
,SOC Physical Design, |
Veena S. Chakravarthi |
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Abstract
This chapter deals with the SOC design as re-convergent model and physical design process of the system on chip (SOC). The complete physical design flow is explained in this chapter starting from floor plan to design tape-out. It defines the re-convergent model of the SOC design and introduces various design file formats which are written out in the physical design. The chapter also deals with the photolithography and pattern transfer from the design tape-out.
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| 11 |
,SOC Physical Design Verification, |
Veena S. Chakravarthi |
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Abstract
This chapter deals with the physical design verification of a system on chip, which are logic equivalence check and STA analysis flow carried out at every stage of the physical design of a SOC. The chapter explains electrical rules checks (ERC), verification of interconnect effects, like cross talk, IR analysis, and the antenna effects. It also deals with design rule checks (DRC) and design for manufacturing (DRM) rules check for the SOC design before the design tape-out to the fabrication house.
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| 12 |
,SOC Packaging, |
Veena S. Chakravarthi |
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Abstract
This chapter deals with packaging of SOC, package architectures, package options available, selection criteria for SOC packages, and package performance.
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| 13 |
,Reference Designs, |
Veena S. Chakravarthi |
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Abstract
This chapter presents a set of design examples which can be tried out on EDA environment. These designs are frequently used blocks which any SOC design would have. It is presented in three sections: Section 1 contains all the small design examples; Section 2 presents a design flow on a counter design with simulation, synthesis, and LEC flow. Also given are extract of dummy design libraries and other files encountered during SOC design. Section 3 presents a head start to a IOT SOC design with requirement capture, design document, and pointer to design database for interested user to work on.
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| 14 |
Back Matter |
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Abstract
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