| 书目名称 | Writing Testbenches using SystemVerilog | | 编辑 | Janick Bergeron | | 视频video | | | 概述 | This is the SystemVerilog version of one of the top selling Springer engineering books ( Writing Testbenches, 1st and 2nd editions).SystemVerilog is the dominant verification language.Verification rem | | 图书封面 |  | | 描述 | If you survey hardware design groups, you will learn that between 60% and 80% of their effort is dedicated to verification. This may seem unusually large, but I include in "verification" all debugging and correctness checking activities, not just writing and running testbenches. Every time a hardware designer pulls up a waveform viewer, he or she performs a verification task. With today’s ASIC and FPGA sizes and geometries, getting a design to fit and run at speed is no longer the main challenge. It is to get the right design, working as intended, at the right time. Unlike synthesizable coding, there is no particular coding style nor language required for verification. The freedom of using any l- guage that can be interfaced to a simulator and of using any features of that language has produced a wide array of techniques and approaches to verification. The continued absence of constraints and historical shortage of available expertise in verification, c- pled with an apparent under-appreciation of and under-investment in the verification function, has resulted in several different ad hoc approaches. The consequences of an informal, ill-equipped and understaffed verification process | | 出版日期 | Book 2006 | | 关键词 | Generator; SystemVerilog; Verilog; model; modeling; simulation; verification; quality control, reliability, | | 版次 | 1 | | doi | https://doi.org/10.1007/0-387-31275-7 | | isbn_softcover | 978-1-4419-3978-4 | | isbn_ebook | 978-0-387-31275-0 | | copyright | Springer-Verlag US 2006 |
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发表于 2025-3-21 16:27:14
