| 书目名称 | Verilog and SystemVerilog Gotchas | | 副标题 | 101 Common Coding Er | | 编辑 | Stuart Sutherland,Don Mills | | 视频video | | | 概述 | Includes over 100 common coding mistakes that can be made with Verilog and SystemVerilog.Explains the symptoms of the error, the rules that cover the error, and how to avoid the error.Addresses how to | | 图书封面 |  | | 描述 | .In programming, “Gotcha” is a well known term. A gotcha is a language feature, which, if misused, causes unexpected - and, in hardware design, potentially disastrous - behavior. The purpose of this book is to enable engineers to write better Verilog/SystemVerilog design and verification code, and to deliver digital designs to market more quickly...This book shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize these common coding mistakes, and know how to avoid them. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug the errors...This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.. | | 出版日期 | Book 2007 | | 关键词 | Hardware; Potential; RTL; SystemVerilog; Verilog; digital design; modeling; programming; verification | | 版次 | 1 | | doi | https://doi.org/10.1007/978-0-387-71715-9 | | isbn_softcover | 978-1-4419-4402-3 | | isbn_ebook | 978-0-387-71715-9 | | copyright | Springer-Verlag US 2007 |
The information of publication is updating
|
|
发表于 2025-3-21 19:50:50
