Titlebook: VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms; 26th IFIP WG 10.5/IE Nicola Bombieri,Graziano Pra

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Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields,rect the function implemented by the circuit so that it matches the given specification. In our recent work [.], we addressed the problem of rectification of buggy finite field arithmetic circuits. The problems are formulated by means of a set of polynomials (ideals) and solutions are proposed using

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ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code, devices exchange huge amount of information. Different multi-bit error detecting and correcting codes are used for error mitigation in the high speed data communication though it introduces delay and their decoding structures are quite complex. Here we have discussed the implementation of single bi

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Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems,alue as inputs to the driven memristors, we propose that the controller reads the logic value and then applies it in parallel to the driven memristors. We consider two different cases based on the initialization of the memristors to logic-1 at the locations where we want keep the first input memrist

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Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Perfocore architecture designed for simulating a Spiking Neural Network (SNN) in real-time. The problem of neuron-to-core mapping is relevant as a non-efficient allocation may impact real-time and reliability of the SNN execution. We designed a task placement pipeline capable of analysing the network of

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Improved Test Solutions for COTS-Based Systems in Space Applications,nstead of space-qualified ones. However, the adoption of COTS devices and boards requires suitable solutions able to guarantee the same level of dependability. A mix of different solutions can be considered for this purpose. Test techniques play a major role, since they must guarantee that a high pe

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Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique fo speeds for reading and writing operations and CMOS/FinFET fabrication process compatibility. STT-MRAMs may be affected by manufacturing defects, which may be challenging to detect under process variations in deeply scaled semiconductor technologies. Because of this, the importance of test technique

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Assessment of Low-Budget Targeted Cyberattacks Against Power Systems,ystems are expected to become more heavily loaded and operate closer to their stability limits and operating constraints. On top of that, in recent years, cyberattacks against computing systems and networks integrated in the power grid infrastructure are a real and growing threat. Such actions, espe

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Efficient Hardware/Software Co-design for NTRU,attacks performed on quantum computers. In order to prepare for such a quantum threat, electronic systems must integrate efficient and secure post-quantum cryptography which is able to meet the different application requirements and to resist implementation attacks. The NTRU cryptosystem is one of t

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