Titlebook: VLSI Design and Test; 23rd International S Anirban Sengupta,Sudeb Dasgupta,Santosh Kumar Vish Conference proceedings 2019 Springer Nature S

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Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductore centre frequency of the filter is 635 MHz with a bandwidth of 8 MHz which can be used in the broadcasting applications. The noise figure of the filter is 0.16 dB. The filter is designed in UMC 180 nm mixed mode CMOS process.

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On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting targeted supply voltage is 0.5 V. The voltage doubler has been designed and simulated in UMC’s 0.18 .m CMOS technology node. It achieves a peak power conversion efficiency (PCE) of 48% at an input power of −12 dBm for an output DC voltage of 0.5 V, and hence suitable for ultra-low power applications.

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Approximate Computing Based Adder Design for DWT Application The goodness of our design is well justified as it shows marginal reduction in signal to noise ratio with a good reduction of layout area and power. We have used 180 nm technology node in our proposed ASIC design.

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An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits. Further, it is observed that the inductive circuit can provide the charging only for 12 cm, whereas a maximum of up to 1 m can be obtained using resonant frequency. Moreover, an approximate improvement of up to 54.6% can be achieved using more number of turns in the inductive based wireless charging system.

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1865-0929 nalog and mixed signal design; computing architecture and security; hardware design and optimization; low power VLSI and memory design; device modelling; and hardware implementation..978-981-32-9766-1978-981-32-9767-8Series ISSN 1865-0929 Series E-ISSN 1865-0937

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Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementationon have been slow in catching up. There are some layout design requirements unique to Analog layout such as Tiling, Fringe capacitance usage, and Dummy devices insertion for matching. Validation of Analog layout before BE delivery is another area which requires many additional checks owing to unique

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A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifierons at 2.4 GHz. Capacitive cross-coupled (CCC) common gate structure enhances the power added efficiency (PAE) and reduces the total harmonic distortion (THD) of the circuit. The power amplifier, implemented in UMC 180 nm technology, is designed without series harmonic rejection tanks and uses dc fe

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