Titlebook: VLSI 2010 Annual Symposium; Selected papers Nikolaos Voros,Amar Mukherjee,Michael Huebner Conference proceedings 2011 Springer Science+Busi

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Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Modelcurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparabl

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Trust Management Through Hardware Means: Design Concerns and Optimizationsiciency of its public key encryption–decryption unit (RSA encryption–decryption module). In this book chapter, we address these issues by describing a design methodology toward a low hardware resources (small chip covered area) and side channel attack resistant RSA hardware architecture. The describ

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Adaptive Task Migration Policies for Thermal Control in MPSoCshe average temperature of the chip and the thermal gradients with a negligible performance overhead. With our techniques, hot spots and temperature gradients are decreased up to 30% with respect to state-of-the-art thermal management approaches.

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XMSIM: Extensible Memory Simulator for Early Memory Hierarchy Evaluationany subset of the application’s data types, (2) user defined mapping of data to memories, (3) simultaneously simulate multiple memory hierarchy scenarios, (4) immediate feedback to code transformations effect on memory hierarchy behavior, (5) verification utilities for the validation of code transfo

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Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moorels. Recent advances in fluidic-operation scheduling, module placement, droplet routing, pin-constrained chip design, and testing are presented. These CAD techniques allow biochip users to concentrate on the development of nanoscale bioassays, leaving chip optimization and implementation details to d

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Naoya Onizawa,Tomoyoshi Funazaki,Atsushi Matsumoto,Takahiro Hanyu

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Cristina Silvano,William Fornaciari,Gianluca Palermo,Vittorio Zaccaria,Fabrizio Castro,Marcos Martin

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A High Level Synthesis Exploration Framework with Iterative Design Space Partitioninged on a gradient-based pruning technique which efficiently evaluates large portions of the solution space in a quick manner. We show that the proposed exploration approach delivers high quality results, with considerable reductions of the exploration’s runtime in respect to the fully exhaustive approach.