| 书目名称 | The Verilog® Hardware Description Language |
| 编辑 | Donald E. Thomas,Philip R. Moorby |
| 视频video | |
| 图书封面 |  |
| 描述 | xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment (" |
| 出版日期 | Textbook 2002Latest edition |
| 关键词 | Advanced VLSI; Describing digital systems; Formal verification; Hardware; Logic design and simulation; Si |
| 版次 | 5 |
| doi | https://doi.org/10.1007/b116662 |
| isbn_softcover | 978-1-4757-7589-1 |
| isbn_ebook | 978-0-306-47666-2 |
| copyright | Springer Science+Business Media New York 2002 |
发表于 2025-3-21 19:58:16
