| 书目名称 | SystemVerilog for Design Second Edition | | 副标题 | A Guide to Using Sys | | 编辑 | Stuart Sutherland,Simon Davidmann,Peter Flake | | 视频video | | | 概述 | Focuses on the design of SystemVerilog for circuit design engineers.Includes numerous examples and updates that encorporates key elements of IEEE 1364.2001 standard.The adopted syntax and recommendati | | 图书封面 |  | | 描述 | .SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs...The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis...SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language...In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendi | | 出版日期 | Book 2006Latest edition | | 关键词 | Design Guide; Hardware; Hardwarebeschreibungssprache; Interface; Standard; Sutherland; SystemVerilog; Veril | | 版次 | 2 | | doi | https://doi.org/10.1007/0-387-36495-1 | | isbn_softcover | 978-1-4419-4125-1 | | isbn_ebook | 978-0-387-36495-7 | | copyright | Springer-Verlag US 2006 |
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发表于 2025-3-21 17:14:52
