| 书目名称 | SystemVerilog Assertions and Functional Coverage | | 副标题 | Guide to Language, M | | 编辑 | Ashok B. Mehta | | 视频video | | | 概述 | in its entirety the latest IEEE-1800 2012 LRM syntax and semantics.both SystemVerilog Assertions and SystemVerilog Functional Coverage language.and methodologies.Providespractical examples of the what | | 图书封面 |  | | 描述 | .Thisbook provides a hands-on, application-oriented guide to the language andmethodology of both SystemVerilog Assertions and SystemVerilog FunctionalCoverage. Readers will benefit from the step-by-step approach to functionalhardware verification using SystemVerilog Assertions and Functional Coverage,which will enable them to uncover hidden and hard to find bugs, point directlyto the source of the bug, provide for a clean and easy way to model complextiming checks and objectively answer the question ‘have we functionallyverified everything’. Written by a professional end-user of ASIC/SoC/CPU andFPGA design and Verification, this book explains each concept with easy tounderstand examples, simulation logs and applications derived from realprojects. Readers will be empowered to tackle the modeling of complex checkersfor functional verification, thereby drastically reducing their time to designand debug. .This updated second edition addresses the latest functional set releasedin IEEE-1800 (2012) LRM, including numerous additional operators and features.Additionally, many of the Concurrent Assertions/Operators explanations areenhanced, with the addition of more examples and figures..· | | 出版日期 | Book 20162nd edition | | 关键词 | Assertion Based Verification; Design Debug; Functional Hardware verification; IEEE-1800 (2012) LRM; Syst | | 版次 | 2 | | doi | https://doi.org/10.1007/978-3-319-30539-4 | | isbn_softcover | 978-3-319-80833-8 | | isbn_ebook | 978-3-319-30539-4 | | copyright | Springer International Publishing Switzerland 2016 |
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发表于 2025-3-21 19:48:20
