Titlebook: System Level Design from HW/SW to Memory for Embedded Systems; 5th IFIP TC 10 Inter Marcelo Götz,Gunar Schirner,Achim Rettberg Conference p

装勇敢地做

Combining an Iterative State-Based Timing Analysis with a Refinement Checking Techniquecation and implementation level, such that already performed analyses of the system have to be repeated. In this work, we extend our timing analysis with a refinement checking approach, detail when it is appropriate to be used, and compare the analysis times with the computation times to perform the refinement check.

Extemporize

Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systemst, e.g., enables consolidation of various dependent singlecore applications on a multicore platform using full virtualization. Finally, we demonstrate functionality of our concept by an automotive use case from literature.

杂役

cavity

Managing Cache Memory Resources in Adaptive Many-Core Systemse information of external memory access-es as an estimate of the amount of memory required by each application. T Experimental results show that, depending on how the redistribution of memory resources among application occurs, the overall system can improve performance up to 18% and the energy savings can reach up to 20%.