| 书目名称 | Synthesizable VHDL Design for FPGAs |
| 编辑 | Eduardo Augusto Bezerra,Djones Vinicius Lettnin |
| 视频video | |
| 概述 | Introduces the subjects in a very concise format, providing just enough information for the reader to develop their first digital systems in VHDL.Book content based on 20 years of experience teaching |
| 图书封面 |  |
| 描述 | .The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.. |
| 出版日期 | Book 2014 |
| 关键词 | Digital System Design with VHDL; FPGA Internal Organization; Finite State Machines; Seven Segment Decod |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-3-319-02547-6 |
| isbn_softcover | 978-3-319-37733-9 |
| isbn_ebook | 978-3-319-02547-6 |
| copyright | Springer International Publishing Switzerland 2014 |
发表于 2025-3-21 18:53:06
