Titlebook: Smart and Flexible Digital-to-Analog Converters; Georgi Radulov,Patrick Quinn,Arthur H.M. van Roerm Book 2011 Springer Science+Business Me

Cumbersome

Brownian Bridge Based Analysis and Modeling of DAC Linearity, an In-depth Viewthe broad error modeling framework of Chap. 5 by concentrating on the DAC unit current amplitude errors. The main novelty of the presented approach is in the application of the Brownian Bridge (BB) process to precisely describe the INL. This method analyzes the thermometer (unary) and binary DAC arc

仲裁者

运动的我

Analysis of Self-Calibration of Currents, an In-depth Viewsmatch errors in Digital-to-Analog Converters (DACs). The self-calibration components are classified in three groups: self-measurement, error processing algorithm and self-correction (where the addition “self” distinguishes self-correction from the more general term “correction”).

无意

aerobic

压碎

New Redundant Decoder Conceptto unary bits. To efficiently improve basic DAC characteristics, the architecture features redundant output unary codes. The main concept offers two modes of operation. Each mode generates a different unary output, i.e. a different switching sequence for the DAC (MSB) unary analog elements. The corr

亵渎

New High-Level Mapping Conceptcy, as defined in Fig. 9.1, to decouple the error correction from the DAC architecture (at algorithmic level). When multiple parallel sub-DACs implement a common D/A function, there is an intrinsic redundancy hidden in the way how each of the sub-DACs contributes to the common output. The presented

APO

New Harmonic-Distortion-Suppression Method segmentation to create redundant D/A functions, defined around nominally identical sub-DAC entities. Further, the method uses a digital pre-processor to create phase shifted replicas of the input signal that are fed to the sub-DACs. These represent the input arguments for the redundant D/A function

不来

Flexible Digital-to-Analog Converters Conceptg DAC architecture. The architecture is based on a modular design approach that uses unary functional segmentation (i.e. parallel sub-DAC units) to realize flexible design, functionality and performance. The architecture includes circuit redundancy, benefiting from the reduced cost per transistor th

能量守恒