| 书目名称 | Reuse Methodology Manual for System-On-A-Chip Designs | | 编辑 | Michael Keating,Pierre Bricaud | | 视频video | http://file.papertrans.cn/830/829343/829343.mp4 | | 图书封面 |  | | 描述 | Silicon technology now allows us to build chips consisting oftens of millions of transistors. This technology promises new levelsof system integration onto a single chip, but also presentssignificant challenges to the chip designer. As a result, many ASICdevelopers and silicon vendors are re-examining their designmethodologies, searching for ways to make effective use of the hugenumbers of gates now available. .These designers see current design tools and methodologies asinadequate for developing million-gate ASICs from scratch. There isconsiderable pressure to keep design team size and design schedulesconstant while design complexities grow. Tools are not providing theproductivity gains required to keep pace with the increasing gatecounts available from deep submicron technology. Design reuse -the use of pre-designed and pre-verified cores - is the mostpromising opportunity to bridge the gap between available gate-countand designer productivity. ..Reuse Methodology Manual for System-On-A-Chip Designs. outlinesan effective methodology for creating reusable designs for use in aSystem-on-a-Chip (SoC) design methodology. Silicon and tooltechnologies move so quickly that no single meth | | 出版日期 | Book 1998 | | 关键词 | ASIC; RTL; Scratch; integrated circuit; system on chip (SoC); transistor | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4757-2887-3 | | isbn_ebook | 978-1-4757-2887-3 | | copyright | Springer-Verlag US 1998 |
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