Titlebook: Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme; GME/GI/ITG-Fachtagun Bernd Reusch Conference proceedings 1990 Spring

Outshine

有危险

squander

CASCH — ein Scheduling-Algorithmus für „High-Level“-Syntheseden können. Eine Zuordnung der Operationen auf Komponententypen wird erst während des Scheduling getroffen, so daß begrenzt vorhandene oder besonders schnelle Komponenten gezielt eingesetzt werden können.

难听的声音

GENUS

音乐会

consent

Hierarchical Netlist Extraction and Design Rule Check. This allows to verify more complex rules than with separated tools and avoids redundant work. To improve verification, the program preserves the original layout hierarchy: Each cell in the layout is checked only once and then replaced by an abstract, containing all information needed to check the

教唆

吝啬性

Timing Driven Partitioning of Combinational Logicd on the line-of-diffusion layout style are automatically generated, placed and routed. A new timing model for complex gates is discussed which permits a fast pattern independent timing analysis with a deviation of less than 15% and two to three orders of magnitude faster than the exact SPICE simula

定点

Diffusion — An Analytic Procedure Applied to Global Macro Cell Placementule-to-chip boundary overlaps is described. The proposed . procedure, although it is so far applicable only for circuit placement, analytically decides on the parallel moves of all variables (module positions) simultaneously with a global objective. The features allowing multiple parallel moves and