Titlebook: Parallel Processing and Applied Mathematics; 4th International Co Roman Wyrzykowski,Jack Dongarra,Jerzy Waśniewski Conference proceedings 2

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A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters-time reconfigurable multi-processor clusters; each organized around a local shared memory module placed in a common address space. Each memory module is accessed by a local cluster bus and a common inter-cluster bus. Programs are organized accordingly to their macro dataflow graphs in which tasks a

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SASEPA: Simultaneous Allocation and Scheduling with Exclusion and Precedence Relations Algorithmne vision applications. In this sense it deals with the peculiarities of systems which combine generic-type processors with Image Acquisition and Processing Boards. The main goal of the algorithm is total processing time reduction; such are the requirements when we deal with automated industrial ins

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A Greedy Approach for a Time-Dependent Scheduling Problem problem. In the problem the processing time .. of each job is described by a function of the starting time . of the job, .. = 1+α.., where α. > 0 for . = 0,1, 2,..., . Jobs are non-preemptable and independent, there are neither ready times nor deadlines, and the criterion of optimality is the total

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Task Scheduling for Dynamically Configurable Multiple SMP Clusters Based on Extended DSC Approachs. A cluster contains processors with data caches connected to a data memory module by an internal cluster bus. Each data memory module is also accessible for a global inter-cluster bus that is available for all processors. Execution of tasks in a processor is done according to a specific macro data