| 书目名称 | Optimal VLSI Architectural Synthesis |
| 副标题 | Area, Performance an |
| 编辑 | Catherine H. Gebotys,Mohamed I. Elmasry |
| 视频video | |
| 丛书名称 | The Springer International Series in Engineering and Computer Science |
| 图书封面 |  |
| 描述 | Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as techno |
| 出版日期 | Book 1992 |
| 关键词 | VLSI; algorithms; analog; architecture; complexity; computer; design process; filter; integrated circuit; mod |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4615-4018-2 |
| isbn_softcover | 978-1-4613-6797-0 |
| isbn_ebook | 978-1-4615-4018-2Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Kluwer Academic Publishers 1992 |
发表于 2025-3-21 20:07:31
