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Titlebook: Networks on Chip; Axel Jantsch,Hannu Tenhunen Book 2003 Springer Science+Business Media New York 2003 VLSI.architecture.computer.computer

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发表于 2025-3-21 17:08:23 | 显示全部楼层 |阅读模式
书目名称Networks on Chip
编辑Axel Jantsch,Hannu Tenhunen
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图书封面Titlebook: Networks on Chip;  Axel Jantsch,Hannu Tenhunen Book 2003 Springer Science+Business Media New York 2003 VLSI.architecture.computer.computer
描述.As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation. .
出版日期Book 2003
关键词VLSI; architecture; computer; computer architecture; distributed systems; operating system; processor
版次1
doihttps://doi.org/10.1007/b105353
isbn_softcover978-1-4419-5344-5
isbn_ebook978-0-306-48727-9
copyrightSpringer Science+Business Media New York 2003
The information of publication is updating

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Multi-Level Software Validation for NoCThis chapter presents a problem in conventional methods of validating software design for NoC: software validation at different abstraction levels. As a solution to resolve the problem, a method of multi-level software validation is explained.
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A Design Methodology for NOC-Based Systemshitecture. The NOC backbone encapsulates the physical integration problems into communication solution for system architect. The NOC platform provides application area optimized computation and storage resources for system developers. Essential parts of the methodology are decision-support methods for both NOC platform and NOC system designers.
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Guaranteeing the Quality of Services in Networks on Chip guaranteed and best-effort (no commitment) services combines their respective attractive features: predictable behaviour, and good average resource utilisation. The . NOC is an example of this approach, and forms the basis of a QoS-based design style, as advocated in this chapter.
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On Packet Switched Networks for On-Chip Communicationtch design, design of network access by cores and communication protocols. A particular protocol stack, called Nostrum, is described as a case study of protocols for on-chip communication. Ideas and tools can be borrowed from computer networks for evaluating on-chip networks.
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Clocking Strategies for Networks-on-Chiproposed over the years and are suitable for the NoC scheme as well as presenting a new and clever way of distributing a Quasi-synchronous, i.e., a perfectly synchronous, but not skew-less, clock across an entire NoC-chip.
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