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Titlebook: Near Threshold Computing; Technology, Methods Michael Hübner,Cristina Silvano Book 2016 Springer International Publishing Switzerland 2016

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Many-Core Architecture for NTC: Energy Efficiency from the Ground Uple cores and substantial memory on the die. However, to construct such a chip, we need to fundamentally rethink the whole compute stack from the ground up for energy efficiency. First of all, we need techniques that minimize and tolerate process variation. It is also important to conceive highly-eff
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Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architetecture is custom designed to operate correctly in Near-Threshold voltages, at sub 500 mV in 65 nm technology while tolerating a large number of Manufacturing Process Variation induced defects. Based on a smart relocation and resizing methodology, RDC-Cache decomposes the data that is targeted for a
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Book 2016 Readers will be enabled with specific techniques to design chips that are extremely robust; tolerating variability and resilient against errors. Variability-aware voltage and frequency allocation schemes will be presented that will provide performance guarantees, when moving toward near-threshold m
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