书目名称 | Low-Power Variation-Tolerant Design in Nanometer Silicon |
编辑 | Swarup Bhunia,Saibal Mukhopadhyay |
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概述 | Presents important challenges in nanometer scale integrated circuit design.Presents a holistic view of Low-Power Variation-Tolerant Design.Covers modeling, analysis and design methodology for low powe |
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描述 | Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes. |
出版日期 | Book 2011 |
关键词 | DFM; Design for Manufacturing; EDA; Electronic Design Automation; Integrated Circuit Design; Low Power IC |
版次 | 1 |
doi | https://doi.org/10.1007/978-1-4419-7418-1 |
isbn_softcover | 978-1-4899-8157-8 |
isbn_ebook | 978-1-4419-7418-1 |
copyright | Springer Science+Business Media, LLC 2011 |