| 书目名称 | Low-Noise Low-Power Design for Phase-Locked Loops |
| 副标题 | Multi-Phase High-Per |
| 编辑 | Feng Zhao,Fa Foster Dai |
| 视频video | http://file.papertrans.cn/589/588880/588880.mp4 |
| 概述 | Provides detailed introduction to noise reduction techniques for fractional-N phase-locked loop systems.Analyzes the nonlinear effect and its impact on fractional-N phase-locked loop systems.Describes |
| 图书封面 |  |
| 描述 | .This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters. . |
| 出版日期 | Book 2015 |
| 关键词 | Clock Generation for Wireless Communication; Frequency Synthesis for Phase-Locked Loops; Low Power Des |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-3-319-12200-7 |
| isbn_softcover | 978-3-319-34370-9 |
| isbn_ebook | 978-3-319-12200-7 |
| copyright | Springer International Publishing Switzerland 2015 |
|Archiver|手机版|小黑屋|
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