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Titlebook: Low Power Methodology Manual; For System-on-Chip D Michael Keating,David Flynn,Kaijian Shi Book 2007 Springer-Verlag US 2007 Aitken.Keating

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书目名称Low Power Methodology Manual
副标题For System-on-Chip D
编辑Michael Keating,David Flynn,Kaijian Shi
视频video
概述Provides practical implementation guidelines for the practicing engineer.Explains key decisions that need to be made in implementing low power designs, why they were made and what results were obtaine
丛书名称Integrated Circuits and Systems
图书封面Titlebook: Low Power Methodology Manual; For System-on-Chip D Michael Keating,David Flynn,Kaijian Shi Book 2007 Springer-Verlag US 2007 Aitken.Keating
描述.“Tools alone aren‘t enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach.”..Richard Goering, Software Editor, EE Times..“Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion.” ..Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies..“The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs.”..Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc...“Managing power, at 90nm and below, introduce
出版日期Book 2007
关键词Aitken; Keating; Low Power Methodology; SoC; Software; Standard; System-on-Chip; UPF; development; network; po
版次1
doihttps://doi.org/10.1007/978-0-387-71819-4
isbn_softcover978-1-4419-4418-4
isbn_ebook978-0-387-71819-4Series ISSN 1558-9412 Series E-ISSN 1558-9420
issn_series 1558-9412
copyrightSpringer-Verlag US 2007
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Multi-Voltage Design,The techniques discussed in the previous chapter are mature; engineers have been using them for some time, and design tools have supported them for years. With this chapter, we begin discussing more recent and aggressive approaches to reducing power: power gating and adaptive voltage scaling.
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Power Gating Overview,Leakage power dissipation grows with every generation of CMOS process technology. This leakage power is not only a serious challenge to battery powered or portable products but increasingly an issue that has to be addressed in tethered equipment such as servers, routers, and set-top boxes.
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Designing Power Gating,This chapter describes power gating design from a front-end, RTL perspective. Figure 5-1 shows the critical components of such a design.
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A Power Gating Example,The SALT technology demonstrator project provided a platform for testing the approaches to power gating and state retention described in this book. In this chapter we give some more details on the system design and RTL coding for this project.
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Frequency and Voltage Scaling Design,Scaling the supply voltage of CMOS is possible over a technology-specific range; gate delays, setup and hold times and even memory access times scale monotonically with reduced operating voltage over a limited range. Linear voltage reduction results in a square-law reduction in both dynamic power consumption and in leakage power.
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