Titlebook: Logic Synthesis and Optimization; Tsutomu Sasao Book 1993 Springer Science+Business Media New York 1993 CAD.FPGA.FPGA design.Field Program

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And-Exor Expressions and their Optimization,eed-Muller expressions, Kronecker expressions, pseudo Reed-Muller expressions, pseudo Kronecker expressions, generalized Reed-Muller expressions and exclusive-or sum-of-products expressions (ESOPs). Relations between these classes are shown. The number of products to realize several classes of funct

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A New Technology Mapping Method Based on Concurrent Factorization and Mapping,hree steps: factorization, cell selection and estimation of constraints. By taking the close relationship of these three steps into account, this method can accommodate detailed constraints because the information in the technology library is accessed during the mapping as well as during the factori

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Gate Sizing for Cell-Based Designs,ch to the gate sizing problem in cell-based logic designs. Our algorithm picks from the cell library one out of several functionally-identical cells for every gate of a combinational Boolean logic circuit so that the circuit delay meets a user-specified constraint while the total gate size is minimi

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Delay Models and Exact Timing Analysis,ay model there is a natural time quantum such that on each integer-multiple bounded interval of the quantum every signal is a constant. Algorithms for exact delay computation for both floating mode and transition mode delay are given. An implementation for the floating mode model yields practical results on large benchmark circuits.

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And-Exor Expressions and their Optimization,ng ternary decision diagrams (TDDs). The conventional method requires memory of O(3.) to simplify an n-variable expression, and is only practical for functions of up to n = 14 variables. The method presented here uses TDDs, and can optimize considerably larger problems. Experimental results for up to n = 39 variables are shown.

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