书目名称 | Logic Synthesis Using Synopsys® | 编辑 | Pran Kurup,Taher Abbasi | 视频video | | 图书封面 |  | 描述 | Logic synthesis has become a fundamental component of the ASICdesign flow, and .Logic Synthesis Using Synopsys.® has beenwritten for all those who dislike reading manuals but who still liketo learn logic synthesis as practised in the real world. The primaryfocus of the book is .Synopsys Design Compiler®:. the leadingsynthesis tool in the EDA marketplace. The book is specially organizedto assist designers accustomed to schematic capture based design todevelop the required expertise to effectively use the Compiler. Over100 `classic scenarios‘ faced by designers using the Design Compilerhave been captured and discussed, and solutions provided. Thescenarios are based both on personal experiences and actual userqueries. A general understanding of the problem-solving techniquesprovided will help the reader debug similar and more complicatedproblems. Furthermore, several examples and dc.-.shellscripts are provided. .Specifically, .Logic Synthesis Using Synopsys.® will help thereader develop a better understanding of the synthesis design flow,optimization strategies using the Design Compiler, test insertionusing the Test Compiler®, commonly used interface formats such asEDIF and SDF, and d | 出版日期 | Book 1995 | 关键词 | VHDL; Verilog; computer-aided design (CAD); design; logic; model; simulation; stability | 版次 | 1 | doi | https://doi.org/10.1007/978-1-4757-2370-0 | isbn_ebook | 978-1-4757-2370-0 | copyright | Springer-Verlag US 1995 |
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