Titlebook: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation; 22nd International W José L. Ayala,Delong Sha

新石器时代

书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation影响因子(影响力)




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation影响因子(影响力)学科排名




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation网络公开度




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation网络公开度学科排名




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation被引频次




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation被引频次学科排名




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation年度引用




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation年度引用学科排名




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation读者反馈




书目名称Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation读者反馈学科排名

Chemotherapy

Pedagogy

Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths,t, only statistical information of the input-stream is needed. The errors of the estimated Hamming and signal distance properties are in the range of 5% to 14% The result of an estimation is available nearly instantaneously since look-up tables are used for implementation.

灯丝

Direct Statistical Simulation of Timing Properties in Sequential Circuits,is is achieved by solving a system of random differential equations (RDE), thus avoiding time-consuming Monte Carlo simulations. The conducted experiments show the accurate calculation of crossing time statistical moments for several sequential cells using 45nm CMOS technology.

Ischemic-Stroke

NAVEN

An Extended Metastability Simulation Method for Synchronizer Characterization,on simulation method are unable to predict correct synchronizer parameters in deep sub-micron technologies. We propose an extended simulation method to estimate synchronizer characteristics more reliably and compare the results obtained with other state-of-the-art simulation methods and with measurements of a 65nm LP CMOS test-chip.

无孔

发芽

Adaptive Synchronization for DVFS Applications,ncy by evaluating flip-flop synchronization performance dynamically. The proposed design meets a reliability criterion without relying on excessively-conservative synchronizers to accommodate for worst-case performance.

Panacea

Muller C-Element Metastability Containment,ult tolerance considerations require relaxing the timing closure. Therefore, this paper studies the vulnerability of asynchronous circuits to metastability at the example of a Muller-C element. Traditional mitigation techniques are applied to this kind of circuits and their fitness for Muller-C elements is analyzed.

Intervention