| 书目名称 | Higher-Level Hardware Synthesis |
| 编辑 | Richard Sharp |
| 视频video | http://file.papertrans.cn/427/426988/426988.mp4 |
| 概述 | Includes supplementary material: |
| 丛书名称 | Lecture Notes in Computer Science |
| 图书封面 |  |
| 描述 | In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its “unrealistic optimism,” Moore’s prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore’s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhar |
| 出版日期 | Book 2004 |
| 关键词 | Hardware; SAFL; VHDL; VLSI specifications; Verilog; compiler; complexity; functional languages; hardware des |
| 版次 | 1 |
| doi | https://doi.org/10.1007/b95732 |
| isbn_softcover | 978-3-540-21306-2 |
| isbn_ebook | 978-3-540-24657-2Series ISSN 0302-9743 Series E-ISSN 1611-3349 |
| issn_series | 0302-9743 |
| copyright | Springer-Verlag Berlin Heidelberg 2004 |
|Archiver|手机版|小黑屋|
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