Titlebook: High — Level Synthesis; Introduction to Chip Daniel D. Gajski,Nikil D. Dutt,Steve Y-L Lin Book 1992 Springer Science+Business Media New Yor

上釉彩

Scheduling, an internal data representation such as the control/data flow graph (CDFG), which captures all the control and data-flow dependencies of the given behavioral description. Scheduling algorithms then partition this CDFG into subgraphs so that each subgraph is executed in one control step. Each contro

AUGUR

Allocation, transfers that can be described by a state table. A target architecture for such a description is the FSMD given in Chapter 2. We derive the control unit for such a FSMD from the control-step sequence and the conditions used to determine the next control step in the sequence. The datapath is derive

omnibus

attenuate

Architectural Models in Synthesis,precisely in terms of particular units, their parameters, and the connections among units. For example, a processor architecture would include the number of registers in the register file, the number of buses in the datapath, the number of pipeline stages, the number of status bits, the number of ways branching can occur, and so on.

Parabola

Scheduling,l step corresponds to one state of the controlling finite-state machine in the FSMD model defined in Chapter 2. In the CDFG of the shift-and-add multiplier (Figure 5.3) dashed lines define the control step boundaries, and operations between two adjacent dashed lines are performed in the same control step.

compassion

Mosaic

flamboyant

免除责任

Partitioning, to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. It can also be used to divide a large design into several chips to satisfy packaging constraints.

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