Titlebook: High Performance Embedded Architectures and Compilers; 5th International Co Yale N. Patt,Pierfrancesco Foglia,Xavier Martorell Conference p

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Low-Overhead, High-Speed Multi-core Barrier Synchronizationevant even for general-purpose CMPs. While the nature of CMP applications requires low-latency, the cost of low-latency barrier implementations using hardware-based techniques can be prohibitive for CMPs, where die area represents opportunities for throughput and yield. Similarly, whereas traditiona

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Obituary

Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors-point streams. The stream compiler statically allocates these kernels to processors, applying blocking, fission and fusion transformations. The compiler determines the sizes of the communication buffers, which affects performance since local memories can be small..In this paper, we propose a feedba

Working-Memory

Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architecturesvel parallelism and memory hierarchy. Sparse matrix computations frequently arise in scientific applications, for example, when solving PDEs on unstructured grids. However, traditional sparse matrix algorithms are difficult to efficiently parallelize for GPUs due to irregular patterns of memory refe

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Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set E-controlled memories accessible exclusively to the ISEs. Unfortunately, the usage of AVS memories creates a coherence problem with the data cache. A multiprocessor coherence protocol can solve the problem, however, this is an expensive solution when applied in a uniprocessor context. Instead, we can

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Accelerating XML Query Matching through Custom Stack Generation on FPGAsed to the current XML-enabled systems. Here, users pose complex queries (expressed in XPath) on the structure and content of the streaming documents. The parts of the documents that match the user queries are then returned to the users. This paper proposes a novel hardware architecture that would ex

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