Titlebook: Emerging VLSI Devices, Circuits and Architectures; Proceedings of the 2 Anu Gupta,Jai Gopal Pandey,Devesh Dwivedi Conference proceedings 20

高射炮

Resistance

A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology,-Digital converter (TDC) under test. This circuit technique avoids the use of costly sophisticated instruments which are required for the measurement of high-speed clocks. The time resolution, i.e. 5 ps is verified using input clocks at 25 MHz.

alcohol-abuse

,High-Precision Programmable Thermistor Linearization ASIC for Electro-Optical Payload Applications, .C to 125 .C. The design also includes the current trimming feature through an external resistor to cater to the requirements of different types of thermistors. The circuit has been designed using a 0.18 .m CMOS process.

军械库

SLAY

https://doi.org/10.1007/978-3-540-31292-5 leakage between adjacent stages of clock booster is prevented with the help of a circuit that blocks the reverse flowing charges. The simulation results show that the proposed circuit gives an output more than 1 V while for similar conditions a conventional clock booster provides less than 500 mV.

BRINK

monopoly

粉笔

E. Edmund Kim,Edward F. Jacksonogether to tune the inductance and hence the operating range of frequency. The proposed AI is designed using CMOS 180 nm technology and simulation shows that for 3–4 GHz frequency range ranging from 13-15nH. The Q-factor and inductance at 3.6 GHz operating frequency is 1750 and 14nH. At 1.8 V supply it dissipates 3.8 mW of power.

Compatriot

https://doi.org/10.1007/978-3-031-35098-6r supply, with a power consumption of 754 µW. The proposed MREC works in the MHz range and the maximum working frequency is 25 MHz. To assess the flexibility of the proposed MREC during circuit employment, two memristors were connected in parallel and performance was compared with a single memristor.

asthma

Results and Problems in Cell DifferentiationThe total power consumption of the circuit is found to be 57 nW and achieves FoM of 336 fJ/conversion for 7 bits of operation with a power supply of 0.5 V. The proposed design has the lowest power consumption and FoM among the reported current mode and neuromorphic ADCs.