Titlebook: Euro-Par 2010, Parallel Processing Workshops; HeteroPAR, HPCC, HiB Mario R. Guarracino,Frédéric Vivien,Michael Alexan Conference proceeding

AXIS

Mucosa

MAHEVE: An Efficient Reliable Mapping of Asynchronous Iterative Applications on Volatile and Heterognt mapping of application tasks is essential to reduce their execution time. In this paper we present a new mapping algorithm, called MAHEVE (Mapping Algorithm for HEterogeneous and Volatile Environments) which is efficient on such architectures and integrates a fault tolerance mechanism to resist c

道学气

Dynamic Load Balancing of Parallel Computational Iterative Routines on Platforms with Memory Heterogat they may fail for large problem sizes on computational clusters with memory heterogeneity. Traditional algorithms use too simplistic models of processors performance which cannot reflect many aspects of heterogeneity. This paper presents a new dynamic load balancing algorithm based on the advance

Tailor

ERUPT

不给啤

HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chipr high performance and power efficiency for general purpose, mainstream computing. While many general-purpose architectures with a moderate number of processing cores are already on the market, architectures with much more significant on-chip parallelism are generally expected, as is already seen fo

faultfinder

The Massively Parallel Computing Model GCA links to its local neighbors, in the GCA model each cell is connected via data dependent dynamic links to any (global) cell of the whole array. The GCA cell state does not only contain data information but also link information. The cell state is synchronously updated according to a local rule, mod

四目在模仿

Armory

Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPsds of cores on-chip. Most likely, some of these many-core CMPs will implement the hardware-managed, implicitly-addressed, coherent caches memory model. Cache coherence in these designs will be probably maintained through a directory-based cache coherence protocol implemented in hardware. The organiz

Ataxia

A Work Stealing Scheduler for Parallel Loops on Shared Cache Multicores requires a careful design of the algorithm in order to keep the locality of the sequential execution. In this paper, we aim at finding a good parallelization of memory bounded applications on multicore that preserves the advantage of a shared cache. We focus on sequential applications with iteratio