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派博传思国际中心 »期刊书目

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› BOOKS with Alphabet E (Ea, Eb,Ec, Ed, Ee…... )

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Titlebook: Enhanced Virtual Prototyping; Featuring RISC-V Cas Vladimir Herdt,Daniel Große,Rolf Drechsler Book 2021 The Editor(s) (if applicable) and T

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发表于 2025-3-21 18:48:15 | 显示全部楼层 |阅读模式
书目名称Enhanced Virtual Prototyping
副标题Featuring RISC-V Cas
编辑Vladimir Herdt,Daniel Große,Rolf Drechsler
视频videohttp://file.papertrans.cn/312/311264/311264.mp4
概述Provides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow.Includes automated formal verification methods and advanced coverage-guided testing
图书封面Titlebook: Enhanced Virtual Prototyping; Featuring RISC-V Cas Vladimir Herdt,Daniel Große,Rolf Drechsler Book 2021 The Editor(s) (if applicable) and T
描述.This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects..
出版日期Book 2021
关键词Virtual Prototypes at the Electronic System Level; SystemC-based Virtual Prototypes; Formal verificati
版次1
doihttps://doi.org/10.1007/978-3-030-54828-5
isbn_softcover978-3-030-54830-8
isbn_ebook978-3-030-54828-5
copyrightThe Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerl
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https://doi.org/10.1007/978-3-030-28936-2), which is the language of choice to create Virtual Prototypes (VPs). Then, the main concepts of the RISC-V Instruction Set Architecture (ISA) are described. RISC-V is used in several evaluations and case studies in this book and is the ISA implemented in our proposed open-source RISC-V based VP. F
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https://doi.org/10.1007/978-94-6091-478-2the RISC-V ecosystem. The VP provides a 32/64 bit RISC-V core with an essential set of peripherals and support for multi-core simulations. In addition, the VP also provides SW debug (through the Eclipse IDE) and coverage measurement capabilities and supports the FreeRTOS, Zephyr and Linux operating
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https://doi.org/10.1057/9780230288843ethods, which may still be susceptible to state space explosion. Compared to the existing simulation-based verification flow this chapter investigates stronger coverage metrics as well as advanced automated test-case generation and refinement techniques. In particular it considers the Data Flow Test
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https://doi.org/10.1057/9780230274907tion flow by integrating stronger coverage metrics and providing automated test-case generation techniques as well as leverage formal methods. Ensuring correct functional behavior is very important to avoid errors and security vulnerabilities (such as buffer overflows). The first approach integrates
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Performance of Labour Managed Firmsr management (PM) strategies can contribute a great deal to the overall power saving by putting unused components into low-power states and waking them up properly in an intelligent manner. Due to its ease of use and flexibility PW strategies are often implemented in SW. PM strategies are analyzed b
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