Titlebook: Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors; Hans Reyserhove,Wim Dehaene Book 2019 Springer Nature Switzer

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Book 2019tectures. The result is a set of techniques and a context to realize minimum energy digital systems. Several prototype silicon implementations are discussed, which put the proposed techniques to the test. The achieved results demonstrate an extraordinary combination of variation-resilience, high speed performance and ultra-low energy..

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Near-Threshold Operation: Technology, Building Blocks and Architecture,he VLSI design methodology motivates us to use sequential clock edge triggered pipelines. The flip-flop building block used in this work is briefly discussed in Sect. 2.3, together with some considerations on how it impacts the microcontroller prototypes..Architectural properties of a digital system

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Error Detection and Correction, with most circuits, this results in an overhead. The circuit is over-designed to make the slowest pipeline stage meet the target operating frequency under the worst conditions. The consequences are a reduced maximum clock frequency and/or increased total energy consumption. Under nominal conditions

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Timing Error-Aware Microcontroller,sparency window that allows error masking similar to a latch. This way, data arriving after the clock can still propagate correctly while being flagged as timing errors. A system level error processor helps to control the autonomous dynamic voltage scaling loop that realizes point-of-first-failure o

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,Die Wärme und die Verdampfung des Wassers,he VLSI design methodology motivates us to use sequential clock edge triggered pipelines. The flip-flop building block used in this work is briefly discussed in Sect. 2.3, together with some considerations on how it impacts the microcontroller prototypes..Architectural properties of a digital system