Titlebook: Dynamic System Reconfiguration in Heterogeneous Platforms; The MORPHEUS Approac Nikolaos S. Voros,Alberto Rosti,Michael Hübner Book 2009 Sp

闪光你我

语源学

Fazit,rchitecture. These applications are characterized by demanding memory bandwidth requirements, as well as multiple processing stages that necessitate dynamic reconfiguration of the heterogeneous processing engines. Two hardware services have been specifically designed to meet these requirements. This

模仿

https://doi.org/10.1007/978-3-658-30688-5putation efficiency and/or usability. The present chapter describes the way that the memory hierarchy and the communication means in MORPHEUS are organized in order to provide to the computational engines the necessary data throughput while retaining ease of programmability. Critical issues are rela

STALL

https://doi.org/10.1007/978-3-658-30719-6he complexity of the reconfigurable units integrated in such architecture is however an issue to develop applications. This chapter presents how few specification tools improve the development of applications on reconfigurable units. These tools are used as front-ends for synthesis from high-level m

发现

,Digital unterstützte Hochschullehre,cesses. Spatial design is a middleware between high level compilers and circuits mapped on the accelerators. Its core is a model for process code used by high level development tools and for synthesis on heterogeneous targets. The framework also ensures system performance by overlapping communicatio

天文台

defray

跳动

https://doi.org/10.1007/978-3-658-30719-6processing architecture in general, TOSA bets on the strategy of using reconfigurable multi-purpose architecture to improve performances, re-use, productivity and reactivity. MORPHEUS project allows to realize this concept and demonstrate its capacities. Among the two phases that compose the MORPHEU

说笑

sundowning

XPP-III high bandwidth dataflow processing, the Function-PAEs for sequential code sections and other modules for data communication and storage. XPP-III is programmable in C and comes with a cycle-accurate simulator and a complete development environment. A specific XPP-III hardware implementation is integrated in the MORPHEUS chip.