Titlebook: Direct Transistor-Level Layout for Digital Blocks; Prakash Gopalakrishnan,Rob A. Rutenbar Book 2004 Springer Science+Business Media New Yo

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cess portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. .Direct Transistor-Level Layout For Digital Blocks. proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that bet

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Reflexionen zu Nützlichkeit vs. Empathied layout flow demonstrate that our tool achieves 100% routed layouts that average 23% less area. In the next chapter, we describe how our flow is further enhanced to handle timing optimization during placement, to reduce overall circuit delays.

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