| 书目名称 | Digital VLSI Design with Verilog | | 副标题 | A Textbook from Sili | | 编辑 | John Williams | | 视频video | | | 概述 | Covers the entire verilog language.Includes a multiple-lab project in development of a large serialization device.Uses simulation examples to teach the writing of code for correct netlist synthesis.Sh | | 图书封面 |  | | 描述 | Verilog and its usage has come a long way since its original invention in the mid-80s by Phil Moorby. At the time the average design size was around ten thousand gates, and simulation to validate the design was its primary usage. But between then and now designs have increased dramatically in size, and automatic logic synthesis from RTL has become the standard design ?ow for most design. Indeed, the language has evolved and been re-standardized too. Overtheyears,manybookshavebeenwrittenaboutVerilog.Myown,coauthored with Phil Moorby, had the goal of de?ning the language and its usage, providing - amples along the way. It has been updated with ?ve new editions as the language and its usage evolved. However this new book takes a very different and unique view; that of the designer. John Michael Williams has a long history of working and teaching in the ?eld of IC and ASIC design. He brings an indepth presentation of Verilog and how to use it with logic synthesis tools; no other Verilog book has dealt with this topic as deeply as he has. If you need to learn Verilog and get up to speed quickly to use it for synthesis, this book is for you. It is sectioned around a set of lessons includ | | 出版日期 | Book 20081st edition | | 关键词 | HDL; Scheduling; VLSI; simulation; synthesis; verification; verilog | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4020-8446-1 | | isbn_ebook | 978-1-4020-8446-1 | | copyright | Springer Science+Business Media B.V. 2008 |
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发表于 2025-3-21 16:58:36
