| 书目名称 | Digital Logic Design Using Verilog | | 副标题 | Coding and RTL Synth | | 编辑 | Vaibbhav Taraate | | 视频video | | | 概述 | Presents unique ideas to interpret digital logic in the Verilog RTL form.Consists of practical scenarios and issues that are helpful to students and professionals.Covers key case studies in generic fo | | 图书封面 |  | | 描述 | This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make ita useful read for students and hobbyists. | | 出版日期 | Book 2016 | | 关键词 | ASIC RTL; DFT; Digital Circuit Design; LINT; Logic Design; SOC; STA; Verilog HDL; FPGA; Low Power Design; Sync | | 版次 | 1 | | doi | https://doi.org/10.1007/978-81-322-2791-5 | | isbn_softcover | 978-81-322-3838-6 | | isbn_ebook | 978-81-322-2791-5 | | copyright | Springer India 2016 |
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发表于 2025-3-21 16:24:46
