Titlebook: Die-stacking Architecture; Yuan Xie,Jishen Zhao Book 2015 Springer Nature Switzerland AG 2015

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1935-3235 tions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative desi

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1935-3235 o designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.978-3-031-00619-7978-3-031-01747-6Series ISSN 1935-3235 Series E-ISSN 1935-3243

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Kenneth B. Gordon,Eric M. Rudermanromising in developing high-bandwidth, low power graphics memory interface. 3D integration also enlarges the capacity of on-chip memory, which can be employed as the last-level cache, a portion of main memory, or the combination of both.

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Conclusion,romising in developing high-bandwidth, low power graphics memory interface. 3D integration also enlarges the capacity of on-chip memory, which can be employed as the last-level cache, a portion of main memory, or the combination of both.

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Coarse-granularity 3D Processor Design,as caches or even on-chip main memories. Different from the research in the previous section, which focuses on optimizations in the fine-granularity (e.g., wire length reduction), the approaches of this section consider the memories as a whole structure and explore the high-level improvements, such

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