Titlebook: Designing Reliable and Efficient Networks on Chips; Srinivasan Murali Book 2009 Springer Science+Business Media B.V. 2009 Design.Networks

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G20 Entrepreneurship Services Report very high (Wang et al., DATE, 2005). Hence, suitable system-level support to provide efficient fault-tolerant mechanisms for memories will be mandatory to ensure proper operation of future MPSoC designs.

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https://doi.org/10.1007/978-981-16-6787-9In this chapter, we present design level support for handling temporary and permanent errors in the NoCs. We present routing mechanisms that achieve an application-specific reliability level against temporary and permanent failures.

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https://doi.org/10.1007/978-981-16-6787-9In this chapter, we summarize the major contributions of this thesis and show how the NoC design methods and reliability mechanisms are integrated in the design flow.

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Fault-Tolerant Route GenerationIn this chapter, we present design level support for handling temporary and permanent errors in the NoCs. We present routing mechanisms that achieve an application-specific reliability level against temporary and permanent failures.

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Conclusions and Future DirectionsIn this chapter, we summarize the major contributions of this thesis and show how the NoC design methods and reliability mechanisms are integrated in the design flow.

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Srinivasan MuraliFirst book that presents in depth the state-of-the-art algorithms and optimization models for performing system-level design of NoCs.Presents an integrated flow to design interconnect architectures th

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Lecture Notes in Electrical Engineeringhttp://image.papertrans.cn/d/image/268985.jpg