书目名称 | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs |
编辑 | Brandon Noia,Krishnendu Chakrabarty |
视频video | http://file.papertrans.cn/269/268878/268878.mp4 |
概述 | Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs.Includes in-depth explanation of key test and design-for-test technologies, emerging standard |
图书封面 |  |
描述 | This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. . |
出版日期 | Book 2014 |
关键词 | 3D Built-in Seft Test; 3D IC Test; 3D Integrated Circuit Design; 3D Memory Test; BIST for TSVs; Through-S |
版次 | 1 |
doi | https://doi.org/10.1007/978-3-319-02378-6 |
isbn_softcover | 978-3-319-34534-5 |
isbn_ebook | 978-3-319-02378-6 |
copyright | Springer International Publishing Switzerland 2014 |