Titlebook: Dependable Computing for Critical Applications; Algirdas Avižienis,Jean-Claude Laprie Textbook 1991 Springer-Verlag/Wien 1991 computer.des

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Dependable Computing for Critical Applications978-3-7091-9123-1Series ISSN 0932-5581

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Krzysztof Wilmański,Bettina Albersvide a standard framework within which to design, build, and assess dependable computing systems. The recent introduction of the European Product Liability Laws has acted as a catalyst in this area..This paper is a survey of the approaches being taken by various important organisations within the UK

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Harald Ehrentraut,Agnieszka Chrzanowskarogram by test samples which are randomly selected based on a defined probability distribution of the input data. The first part of the paper provides a short view of the current state of investigation in statistical testing area. Then a comparison of the strengths and weaknesses of statistical test

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The Concept of Dynamic Stabilityl of safety and reliability are given. Next,two types of microcomputer architectures with hardware redundancy are shown. Safety methods for a video display unit and data transmission are also given. Fault-tolerant system structures with triple-modular-redundancy, duplex and single,which have been ap

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András Prékopa,Jianmin Long,Tamás Szántai are the Airbus and the ATR By studying the evolution of these aircraft families, it can be seen that digital computing systems are becoming increasingly numerous and used in increasingly critical functions Aerospatiale has therefore had to adapt its design and certification methods to suit. A lesso

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Dynamic Stochastic Optimizationor commercial use, many fault-tolerance concepts are systematically combined. Besides adopting the conventional approaches such as spatial diversity based on the majority voting, the usage of ECC, watch dog timers and current limiter, we introduce some new concepts such as softwarevoting with inter-

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Dynamic Stochastic Optimization7 and 757 aircrafts. A hierarchical simulation environment based on SPLICE which allows the injection of transients during run-time and, the tracing of their impact is described. Results show that given a transient fault, there is approximately an 80% chance that there is no impact on the chip. If n

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