| 书目名称 | Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits |
| 编辑 | Manoj Sachdev,José Pineda de Gyvez |
| 视频video | |
| 概述 | Wide coverage of topics in test engineering.Unique defect-oriented focus of the materials.Introduction to yield engineering common practices |
| 丛书名称 | Frontiers in Electronic Testing |
| 图书封面 |  |
| 描述 | Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device |
| 出版日期 | Book 2007Latest edition |
| 关键词 | CMOS; DSM; DfM; RAM; SRAM; VLSI; defects; integrated circuit; logic; testing; yield |
| 版次 | 2 |
| doi | https://doi.org/10.1007/0-387-46547-2 |
| isbn_softcover | 978-1-4419-4285-2 |
| isbn_ebook | 978-0-387-46547-0Series ISSN 0929-1296 |
| issn_series | 0929-1296 |
| copyright | Springer-Verlag US 2007 |
发表于 2025-3-21 16:27:05
