Titlebook: Cryptographic Hardware and Embedded Systems - CHES 2009; 11th International W Christophe Clavier,Kris Gaj Conference proceedings 2009 © Int

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An Efficient Method for Random Delay Generation in Embedded Softwaremethod for generation of random delays and a criterion for measuring the efficiency of a random delay countermeasure. We implement this new method along with the existing ones on an 8-bit platform and mount practical side-channel attacks against the implementations. We show that the new method is si

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Higher-Order Masking and Shuffling for Software Implementations of Block Cipherswo main techniques are usually applied to thwart them: masking and operations shuffling. To benefit from the advantages of the two techniques, recent works have proposed to combine them. However, the schemes which have been designed until now only provide limited resistance levels and some advanced

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A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniquesaphic hardware modules. The original RSL proposed in 2004 requires a unique RSL-gate for random data masking and glitch suppression to prevent secret information leakage through power traces. However, our new methodology enables to use general logic gates supported by standard cell libraries. In ord

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A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensionscted logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with

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Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multiplieic curves. We propose here a novel hardware implementation of Miller’s loop based on a pipelined Karatsuba-Ofman multiplier. Thanks to a careful selection of algorithms for computing the tower field arithmetic associated to the Tate pairing, we manage to keep the pipeline busy. We also describe the

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Faster ,-Arithmetic for Cryptographic Pairings on Barreto-Naehrig CurvesN curves and choose curve parameters such that . multiplication becomes more efficient. The proposed algorithm uses Montgomery reduction in a polynomial ring combined with a coefficient reduction phase using a pseudo-Mersenne number. With this algorithm, the performance of pairings on BN curves can

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Christopher G. Haswell,Jonathan Shachterion that allows to determine the number of the trial divisions for each prime candidate. Practical experiments are conducted, and countermeasures are proposed. For realistic parameters the success probability of our attack is in the order of 10–15 %.