Titlebook: Correct Hardware Design and Verification Methods; IFIP WG 10.2 Advance George J. Milne,Laurence Pierre Conference proceedings 1993 Springer

故障

书目名称Correct Hardware Design and Verification Methods影响因子(影响力)




书目名称Correct Hardware Design and Verification Methods影响因子(影响力)学科排名




书目名称Correct Hardware Design and Verification Methods网络公开度




书目名称Correct Hardware Design and Verification Methods网络公开度学科排名




书目名称Correct Hardware Design and Verification Methods被引频次




书目名称Correct Hardware Design and Verification Methods被引频次学科排名




书目名称Correct Hardware Design and Verification Methods年度引用




书目名称Correct Hardware Design and Verification Methods年度引用学科排名




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书目名称Correct Hardware Design and Verification Methods读者反馈学科排名

朴素

Logic verification of incomplete functions and design error location,o be incorrect, a conditional stuck-at fault model is proposed to represent the circuit with design errors. The incorrect logic values at the design error sites can be considered as conditional stuck-at faults. A design error locating method, based on fault simulation and released pattern generation, is described.

河流

A theory of generic interpreters, The generic interpreter theory provides a methodology for deriving important definitions and lemmas that were previously obtained in a largely ad hoc fashion. Many of the complex data and temporal abstractions are done in the abstract theory and need not be redone when the theory is used.

预感

Towards a provably correct hardware implementation of occam,d subset of occam. Algebraic laws are used to facilitate the transformation from a program into a normal form. The compiling specification is presented as a set of theorems that must be proved correct with respect to these laws. A rapid prototype compiler in the form of a logic program may be implemented from these theorems.

cogitate

forthy

forthy

Verification and diagnosis of digital systems by ternary reasoning,ternary simulation. The verification vectors are derived from AND/OR trees. We also show how design error diagnosis can be performed by utilizing the difference vector set. Algorithms for the diagnosis of single inverter errors, and wrong gate type, are presented, together with illustrative examples.

Amenable

A methodology for system-level design for verifiability,scription is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra manipulation supports formal equivalence proofs. Experimental results show that the approach is feasible also for real-size industrial cases.

Postulate

Calculational derivation of a counter with bounded response time,erves as the functional specification..The design is generic in that it describes counters with all possible periods. The response time as well as the power dissipation of all these counters are bounded by values that do not depend on the period.

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