书目名称 | Constraining Designs for Synthesis and Timing Analysis |
副标题 | A Practical Guide to |
编辑 | Sridhar Gangadharan,Sanjay Churiwala |
视频video | http://file.papertrans.cn/236/235919/235919.mp4 |
概述 | Provides a hands-on guide to create constraints for synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.Explains fundamental |
图书封面 |  |
描述 | This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. |
出版日期 | Book 2013 |
关键词 | ASIC; FPGA; Integrated Circuit Design; Placement and Routing; Static Timing Analysis; Synopsys Design Con |
版次 | 1 |
doi | https://doi.org/10.1007/978-1-4614-3269-2 |
isbn_softcover | 978-1-4899-8916-1 |
isbn_ebook | 978-1-4614-3269-2 |
copyright | Springer Science+Business Media New York 2013 |