Titlebook: Concurrency: Theory, Language, and Architecture; UK/Japan Workshop, O Akinori Yonezawa,Takayasu Ito Conference proceedings 1991 Springer-Ve

AVOID

A hierarchical approach to hardware design, is supported with an example..A series of levels of abstraction are indicated, the most interesting of which deal with timing of device observables, and criteria are given for moving between them. One of the techniques considered, ., enables an event to be refined by a sequence of smaller events. U

诱骗

Transformational derivation of systolic arrays,The specifications are described in recurrence equations. A certain sub-class of systolic array architectures can be derived following this approach..In order to apply program transformation to systolic array derivation, we first introduce a subset of concurrent logic language to represent a systoli

斗争

Locally computable coding for unary operations,ts of operands under a coding scheme, we say the operation is locally computable under the coding scheme. There is a closed relation between local computability and redundancy of codes. Several excellent algorithms utilizing local computability by redundant coding schemes are developed and used prac

沙文主义

Reuse of concurrent object descriptions,ly, i.e., two methods in different sorts do not override each other. By this way of separation, synchronization codes can be effectively shared and reused. We present two application examples to show the effectiveness of our technique.

轮流

极深

fulmination

https://doi.org/10.1007/b138484e both how this model is able to capture a wide range of subtle behaviours which have no direct untimed analogues, and how the axioms of the model can be justified by a detailed study of nondeterminism.

implore

https://doi.org/10.1007/b138484such that the model can be checked to satisfy the requirement at each point. A brief overview of executable temporal logic is presented together with a discussion of the advantages of an intuitionistic version. RDL is being developed as a formalism that would be appropriate for AI-based design support in engineering.

意见一致

Keyao Zhu,Hongyue Zhu,Biswanath Mukherjeecution. Fleng is the core language for this language set, on which Fleng++ and Fleng−− are based. Control features for parallel machine such as process allocation, load distribution and memory management are also discussed in relation to this language set.

LINE

Keyao Zhu,Hongyue Zhu,Biswanath Mukherjeefrom a naive semantics suitable for simulation in sequential machines, we develop a new semantics with fine grain parallelism. The semantics is based on the coloring scheme which paints variable substitutions made in each OR-parallel world by distinct colors.