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Titlebook: Computer Architecture Techniques for Power-Efficiency; Stefanos Kaxiras,Margaret Martonosi Book 2008 Springer Nature Switzerland AG 2008

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发表于 2025-3-21 18:26:43 | 显示全部楼层 |阅读模式
书目名称Computer Architecture Techniques for Power-Efficiency
编辑Stefanos Kaxiras,Margaret Martonosi
视频video
丛书名称Synthesis Lectures on Computer Architecture
图书封面Titlebook: Computer Architecture Techniques for Power-Efficiency;  Stefanos Kaxiras,Margaret Martonosi Book 2008 Springer Nature Switzerland AG 2008
描述In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and aslowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power d
出版日期Book 2008
版次1
doihttps://doi.org/10.1007/978-3-031-01721-6
isbn_softcover978-3-031-00593-0
isbn_ebook978-3-031-01721-6Series ISSN 1935-3235 Series E-ISSN 1935-3243
issn_series 1935-3235
copyrightSpringer Nature Switzerland AG 2008
The information of publication is updating

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Computer Architecture Techniques for Power-Efficiency
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Modeling, Simulation, and Measurement,tural techniques. In order to compare these many ideas, quantitative techniques for architecture-level power modeling have become very important. Thus, in this chapter, we discuss some of the key issues and techniques for the field of architecture-level power modeling. This sets the foundation for l
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Optimizing Capacitance and Switching Activity to Reduce Dynamic Power, the dynamic power equation written as: . = . × . × . where ., the ., is the product of . and .. The switching activity factor, a fraction between 0 and 1, simply expresses how much of the circuit’s . capacitance is charged and discharged—on average—during each cycle at the operating frequency ..
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Managing Static (Leakage) Power,s due to the imperfect nature of transistors which “leak” current—thereby constantly consuming power—even when they are not switching. The advent of this form of static power, called ., was forecasted early on [32, 136], giving architects the opportunity to propose techniques to address it. Such tec
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Conclusions,driver of the field in recent years. Both the increase in dynamic power and even more so the exponential increase of static power have brought sweeping changes in the way we design and build processors.
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