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Titlebook: Compiler Construction; 11th International C R. Nigel Horspool Conference proceedings 2002 Springer-Verlag Berlin Heidelberg 2002 Attribut.C

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Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation tests, up to 22% of memory operations are removed. Four registers, for example, are sufficient to reduce the energy-delay product by 7 to 26%. Our results suggest that global variable promotion should be included as a standard optimization technique in power-conscious compilers.
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Conference proceedings 2002s established in 1998by combining a number of existing and new conferences. This year it comprised 5 conferences (FOSSACS, FASE, ESOP, CC, TACAS), 13 satellite workshops (ACL2, AGT, CMCS, COCV, DCC, INT, LDTA, SC, SFEDL, SLAP, SPIN, TPTS, and VISS), 8invited lectures (not including those speci?c to
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Data Compression Transformations for Dynamically Allocated Data Structuress. We have developed the . and . transformations that respectively compress a 32 bit address pointer and a 32 bit integer field into 15 bit entities. A pair of fields which have been compressed by the above compression transformations are packedt ogether into a single 32 bit word. The above transfor
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Evaluating a Demand Driven Technique for Call Graph Constructionere is a need for techniques for demand driven construction of a call graph. We have developed a technique for demand driven call graph construction which handles dynamic calls due to polymorphism in object-oriented languages. Our demand driven technique has the same accuracy as the corresponding ex
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A Graph—Free Approach to Data—Flow Analysisblem, this algorithm computes the maximum fixed point (MFP) solution. The edge structure of the graph represents possible control flows in the program. In this paper, we present a new, graph-free algorithm for computing the MFP solution. The experimental implementation of the algorithm was applied t
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A Representation for Bit Section Based Analysis and Optimizations, or general purpose processors with media extensions. In addition data compression techniques which are vital for embedded system applications result in code operating on subword level as well. Performing analysis on word level, however, is too coarse grain missing opportunities for optimizations.
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