Titlebook: CMOS Processors and Memories; Krzysztof Iniewski Book 2010 Springer Science+Business Media B.V. 2010 CMOS.DRAM.FPGA.Field Programmable Gat

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Low Power Asynchronous Circuit Design: An FFT/IFFT Processor on low voltage operation and low energy dissipation. The circuits designed herein span from microcells (adders and some handcrafted asynchronous basic cells) and macrocells (a multiplier and a memory) to a complete 128-point radix-2 decimation-in-time Fast Fourier Transform/Inverse Fast Fourier Tra

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A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architectureg a variety of disciplines. The field of digital integrated circuit design is one such discipline within which researchers are continually seeking ways of leveraging novel nanoscale technologies to develop next generation circuits and architectures. A major motivating factor for this research is the

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Flash Memory for data storage have been industry-standard products by making the most of each feature, respectively. This chapter will mainly focus on these two types of Flash memory and compare from the view point of memory array architecture and operation schemes (Program, Erase and Read) with discussing reli

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Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities scales down, achieving fast nanosecond time scale magnetization switching and maintaining thermal stability at second to years time scale become increasingly challenging. At the same time, the increased variability due to device dimension shrinking results device performance degradation. In the cha

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Overview and Scaling Prospect of Ferroelectric Memoriesrial, operating principle, and current status of FeRAMs and chain FeRAMs are introduced. Second, several key techniques to achieve stable FeRAM operation and realize FeRAM scaling are described: (1) the scaling techniques to reduce bitline capacitance to obtain sufficient cell signal in scaled FeRAM

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