Titlebook: Automated Technology for Verification and Analysis; 21st International S Étienne André,Jun Sun Conference proceedings 2023 The Editor(s) (i

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Specification Sketching for Linear Temporal Logic engineer’s understanding of the given system. However, this assumption is often unrealistic in practice: formalizing system requirements is notoriously difficult, error-prone, and requires substantial training. To alleviate this hurdle, we propose a novel approach of assisting engineers in writing

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Predicting Memory Demands of BDD Operations Using Maximum Graph Cuts dealing with moderate-sized BDDs. This is mostly due to initializing expensive external memory data structures, even if their contents can fit entirely inside internal memory..The contents of these auxiliary data structures always correspond to a graph cut in an input or output BDD. Specifically, t

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Structure-Guided Solution of Constrained Horn Clauses the set of CHCs. Our technique is driven by the idea that a set of CHCs can be solved in parts, making it an easier problem for the CHC-solver. Furthermore, solving a set of CHCs can benefit from an interpretation revealed by the solver for its subsets. Our technique is . in that it gradually exten

Concrete

Automated Property Directed Self Composition self composition, which reduces the .-safety verification task into a standard (.)safety verification exercise, verifying self-composed programs is not easy. The proofs often require that the functionality of every component program be captured fully, making invariant inference a challenge. Recentl

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Fast Equivalence Checking of Quantum Circuits of Clifford Gatesices. We consider quantum circuits consisting of Clifford gates, a practically-relevant subset of all quantum operations which is large enough to exhibit quantum features such as entanglement and forms the basis of, for example, quantum-error correction and many quantum-network applications. We pres

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